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92706 / 21306 ms ot 20051228-s00001 no.a0287-1/24 http://onsemi.com semiconductor components industries, llc, 2013 may, 2013 lb11693h overview the lb11693h reduces motor noise by imparting a slope to the output current when switching the phase to which power is applied. this motor driver includes an automatic recovery constraint protection circuit and is optimal for driving 24v fan motors. functions ? soft phase switching + direct pwm drive ? pwm control based on both a dc voltage input (the ctl voltage) and a pulse input ? provides a 5 v regulator output ? one hall-effect sensor fg output ? integrating amplifier ? automatic recovery constraint protection circuit (on/off = 1/14), rd output ? current limiter circuit ? lvsd circuit ? thermal protection circuit specifications absolute maximum ratings at ta = 25 c parameter symbol conditions ratings unit supply voltage range v cc max 30 v output current i o max t 500ms 1.8 a allowable power dissipation 1 pd max1 independent ic 0.9 w allowable power dissipation 2 pd max2 when mounted on a circuit board * 2.1 w operating temperature topr -30 to +100 c storage temperature tstg -55 to +150 c *: on the specified circuit board (114.3mm 76.1mm 1.6mm, glass epoxy) allowable operating ranges at ta = 25 c parameter symbol conditions ratings unit supply voltage rang v cc 9.5 to 28 v constant voltage output current i reg 0 to -30 ma rd output current i rd 0 to 10 ma fg output current i fg 0 to 10 ma ordering number : ENA0287 monolithic digital ic 3-phase brushless motor driver for 24v fan motors stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty.
lb11693h no.a0287-2/24 electrical characteristics at ta = 25c, v cc = vm = 24v ratings parameter symbol conditions min typ max unit current drain 1 i cc 1 10 13.5 ma current drain 2 i cc 2 when stop 4.0 5.5 ma output block output saturation voltage 1 v o sat1 i o = 0.7a, v o (sink) + v o (source) 1.5 2.05 v output saturation voltage 2 v o sat2 i o = 1.5a, v o (sink) + v o (source) 2.2 2.9 v output leakage current i o leak 100 a high side diode forward voltage 1 vd1 id = 0.7a 1.25 1.65 v high side diode forward voltage 2 vd2 id = 1.5a 1.9 2.5 v 5v constant voltage output output voltage vreg i o = -5ma 4.7 5.0 5.3 v voltage regulation vreg1 v cc = 9.5 to 28v 30 100 mv load regulation vreg2 i o = -5 to -20ma 20 100 mv hall amplifier input bias current i b (ha) 2 10 a differential input voltage range vhin sine wave input 50 350 mvp-p common-mode input voltage range vicm differential input 50mvp-p 1.5 vreg-1.0 v input offset voltage vioh design target value -20 20 mv csd pin high-level output voltage v oh (csd) 2.75 3.0 3.25 v low-level output voltage v ol (csd) 0.85 1.0 1.15 v external capacitor charge current i csd 1 -3.3 -2.4 -1.4 a external capacitor charge current i csd 2 0.09 0.17 0.23 a charge/discharge current ratio r csd charge current/discharge current 14 times undervoltage protection circuit (lvs pin) operating voltage v sd l 3.6 3.8 4.0 v release voltage v sd h 4.1 4.3 4.5 v hysteresis v sd 0.35 0.5 0.65 v current limiter circuit (rf pin) limiter voltage v rf v cc -vm 0.45 0.5 0.55 v thermal shutdown operation thermal shutdown operating voltage tsd design target value (junction temperature) 150 170 c hysteresis tsd design target value (junction temperature) 40 c ctl amplifier input offset voltage v io (ctl) -10 10 mv input bias current i b (ctl) -1 1 a common-mode input voltage range vicm 0 vreg-1.7 v high-level output voltage v oh (ctl) i toc = -0.2ma vreg-1.2 vreg-0.8 v low-level output voltage v ol (ctl) i toc = 0.2ma 0.8 1.05 v open-loop gain g(ctl) f(ctl) = 1khz 45 51 db continued on next page.
lb11693h no.a0287-3/24 continued from preceding page. ratings parameter symbol conditions min typ max unit pwm oscillator circuit high-level output voltage v oh (pwm) 2.75 3.0 3.25 v low-level output voltage v ol (pwm) 1.1 1.3 1.4 v amplitude v(pwm) 1.5 1.7 2.0 vp-p external capacitor charge current i chg vpwm = 2.1v -125 -90 -70 a oscillator frequency f(pwm) c = 2200pf 15.5 19.5 27.0 khz toc pin input voltage 1 v toc 1 output duty: 100% 2.72 3.0 3.30 v input voltage 2 v toc 2 output duty: 0% 1.07 1.3 1.45 v input voltage 1l v toc 1l design target value. 100% when vreg = 4.7v 2.72 2.80 2.90 v input voltage 2l v toc 2l design target value. 0% when vreg = 4.7v 1.07 1.17 1.27 v input voltage 1h v toc 1h design target value. 100% when vreg = 5.3v 3.08 3.20 3.30 v input voltage 2h v toc 2h design target value. 0% when vreg = 5.3v 1.21 1.33 1.45 v rd pin low-level output voltage v ol (rd) i rd = 5ma 0.1 0.3 v output leakage current i l (rd) v rd = 28v 10 a fg pin low-level output voltage v ol (fg) i fg = 5ma 0.1 0.3 v output leakage current i l (fg) v fg = 28v 10 a fgfil pin charge current i fgfil 1 -7 -5 -3 a discharge current i fgfil 2 3 5 7 a fg amplifier schmitt block (in1) amplifier gain g(fg) design target value. 7 times hysteresis v is (fg) design target value. input equivalent 8 mv s/s pin high-level input voltage v ih (ss) 2.0 vreg v low-level input voltage v il (ss) 0 1.0 v input open voltage v io (ss) 2.6 2.9 3.2 v hysteresis v is (ss) 0.16 0.25 0.34 v high-level input current i ih (ss) vs/s = vreg 100 130 a low-level input current i il (ss) vs/s = 0v -170 -130 a pwmin pin input frequency range f(pi) 50 khz high-level input voltage range v ih (pi) 2.0 vreg v low-level input voltage range v il (pi) 0 1.0 v input open voltage v io (pi) 2.6 2.9 3.2 v hysteresis v is (pi) 0.16 0.25 0.34 v high-level input current i ih (pi) vpwmin = vreg 100 130 a low-level input current i il (pi) vpwmin = 0v -170 -130 a f/r pin high-level input voltage v ih (fr) 2.0 vreg v low-level input voltage v il (fr) 0 1.0 v input open voltage v io (fr) vreg-0.5 vreg v hysteresis v is (fr) 0.16 0.25 0.34 v high-level input current i ih (fr) v fr = vreg -10 0 10 a low-level input current i il (fr) v fr = 0v -165 -115 a
lb11693h no.a0287-4/24 (6.2) 36 1 19 18 0.8 2.0 17.8 0.3 (4.9) 2.7 0.65 0.25 (0.5) 7.9 10.5 (2.25) 2.45max 0.1 sanyo : hsop36r(375mil) package dimensions unit : mm 3251 pin assignment truth table f/r = ?l? f/r = ?h? source sink in1 in2 in3 in1 in2 in3 1 out2 out1 h l h l h l 2 out3 out1 h l l l h h 3 out3 out2 h h l l l h 4 out1 out2 l h l h l h 5 out1 out3 l h h h l l 6 out2 out3 l l h h h l
lb11693h no.a0287-5/24 pin function pin no. symbol description equivalent circuit 34 36 2 out1 out2 out3 motor drive output 4 gnd2 motor drive output system ground 7 vd low side output transistor drive current supply 9 vm motor drive output power supply and output current detection. connect a resistor (rf) between this pin and v cc . the output current is limited to a value determined by the equation i out = v rf /rf. 8 v cc power supply (systems other than the motor drive output) 10 vreg 5v regulator output (control circuit power supply). connect a capacitor (about 0.1f) between this pin and ground for stabilization. 11 lvs undervoltage protection voltage detection. connect this pin to vreg if the vreg level is to be detected. if the v cc level is to be detected, insert a zener diode in series to set the detection level. 12 fgfil fg filter. normally, this ic will be used with this pin open. connect a capacitor between this pin and ground if noise on the fg signal becomes a problem. continued on next page.
lb11693h no.a0287-6/24 continued from preceding page. pin no. symbol description equivalent circuit 14 fc control loop frequency characteristics correction. connect a capacitor between this pin and ground. 15 csd constraint protection circuit operating time setting. 16 fg hall input 1fg output. (this is an open-collector output.) 17 rd motor constrained state detection output (this is an open-collector output.) when the motor is constrained: high, when the motor is turning: low. 18 pwmin pwm pulse input. when low the output will be on and when high the outputs will be off. if this pin is used to control this ic, connect ei - to ground and connect ei + to toc. continued on next page.
lb11693h no.a0287-7/24 continued from preceding page. pin no. symbol description equivalent circuit 20 s/s start/stop control. low: start, high or open: stop. 21 22 ei + ei - ctl amplifier noninverting input ctl amplifier inverting input 23 toc pwm waveform comparator (ctl amplifier output) 25 pwm pwm oscillator frequency setting. connect a capacitor between this pin and ground. a frequency of about 20khz can be set by using a 2200pf capacitor. continued on next page.
lb11693h no.a0287-8/24 continued from preceding page. pin no. symbol description equivalent circuit 26 gnd1 ground (for circuits other than the motor drive output system) 28 27 30 29 32 31 in1 + in1 - in2 + in2 - in3 + in3 - hall effect sensor inputs high when in + > in - , low for the reverse state. signal inputs with an amplitude (differential) of at least 50mvp-p are desirable for the hall inputs. if noise is a problem, connect capacitors between the in + and in - inputs. 33 f/r forward/reverse control low: forward, high or open: reverse. 1,3 5,6 13,1 9 24,3 5 nc no connection. the nc pins may be used for wiring connections. frame frame connection the frame pin is connected internally to the ic surface metal parts. both must be used in the electrically open state.
lb11693h no.a0287-9/24 block diagram
lb11693h no.a0287-10/24 lb11693h overview 1. output drive circuit the lb11693h reduces motor vibration and noise by switching the output current smoothly when switching phases. since the hall input waveform is used for the change in (slope of) the output current during phase switching, if the slope of the hall input waveform is too steep, the change in the output current during phase switching will also be too steep and the effectiveness of this technique at lowering vibr ation and noise effect will be reduced. thus the slope of the hall input waveform requires attention during application design. low side output transistor pwm switching is used for motor speed control. the drive output is adjusted by changing the duty. the diodes between the outputs and vm used for the regenerative current when the pwm signal is in the off state are built in. if the slope (amplitude) of the hall input waveform is large, and if used with a high current, the parasitic diodes between the outputs and ground will operate due to the low si de kickback during phase switching. if problems such as disruption of the waveforms occur, connect either rectifying diodes or schottky diodes between the outputs and ground. 2. power supply stabilization since the lb11693h uses a control method based on pwm switching, the power supply lines are susceptible to disruption. electrolytic capacitors with an adequate ca pacitance for stabilization must be connected between v cc and ground. if diodes are inserted in the power supply lines to pr event destruction of the equipment if the power supply is connected in reverse, the power supply lin es will be particularly susceptible to disruption. in this case, even larger capacitors must be used. the connected el ectrolytic capacitors must be located as close as possible to the ic pins (v cc , vm, and gnd2). if the electrolytic capacitors cannot be attached close to the pins due to problems with the heat sink or other issues, ceramic capacitors of about 0. 1f must be attached close to the pins. 3. vreg pin at the same time as being the 5v regulator output, the vreg pin is also the power supply for the ic internal control circuits. therefore, a capacitor of at least 0.1f must be connected between the vreg pin and ground to stabilize the control circuit power supply. the ground side of the connec ted capacitor must be connected to the gnd1 pin with as short a line as possible. 4. fc pin the capacitor connected to the fc pin is required to correct the control loop's frequency character istics. (it should be about 0.1f.) 5. vd pin the vd pin supplies the low side output transistor drive current (a maximum of about 0.1a). the ic internal power consumption is suppressed by connecting a resistor between the v cc and vd pins and dividing power consumption due to the low side output transistor drive current with that resistor. although the ic internal power consumption due to the drive current can be reduced by lowering the vd pin voltage, a voltage of at least 4 v must be assured at the vd pin. use a resistor in the range from about 50 (0.5w) to about 100 (1w) between the v cc and vd pins when the lb11693h is used with v cc = 24v. 6. hall input signals signal inputs with an amplitude (differential) of at l east 50mvp-p are required for the hall inputs. if the output waveforms are disrupted by noise, capacitors must be c onnected between the hall input pins (the + and - sides). 7. current limiter circuit the current limiter circuit limits the peak value of the out put current to a current determined by the equation i = v rf /rf (where v rf = 0.5v (typical), rf = current detection resistor value). when the limiter operates, it suppresses the current by pwm control of the low side output transi stor at the pwm frequency de termined by the external capacitor connected to the pw m pin, in particular, by reducing the on duty.
lb11693h no.a0287-11/24 8. forward/reverse switching the lb11693h was designed assuming that forward/reverse switching would not be performed while the motor is operating. we recommend that the f/r pin be held fixed at either the low (forward) or high (reverse) level when the motor is turning. although it will be pulled up to the high level by an internal pull-up resistor (about 40k ) when left open, this must be strengthened by an external resistor if fluctuations are large. if the direction is switched while the motor is turning, la rge currents will flow due to the braking operation. the lb11693h's current limiter circuit, howe ver, cannot limit this braking current. therefore, forward/reverse switching during motor rotation is only possible if the braking current is limited to a value under i o max (1.8a) by the motor coil resistance or other circuit or phenomenon. furthermore, since through current will flow in the high and low side transistors at the instant the switch occurs with switching th at only uses the f/r pin, app lications must provide a drive off period for switching directions. a drive off period must be provided by either setting the ic to the stopped state with the s/s pin or setting the pwm signal to the 0% duty state with the toc and pwmin pins, and the f/r pin must only be switched during that period to prevent through current. 9. power saving circuit this ic can be set to a power saving state in which current consumption is reduced by setting it to the stopped state with the s/s pin. the bias current to most of the circuits in the ic is cut off in this power saving state. note, however, that the 5v regulator output is still provided in the power saving state. 10. notes on the pwm frequency the pwm frequency is determined by the capacitance (f) of the cap acitor connected to the pwm pin. fpwm 1/(23400 c) a frequency in the range 15 to 25khz is desirable for the pwm frequency. the ground si de of the connected capacitor must be connected to the gnd1 pi n by as short a line as possible. 11. control methods the output duty can be controlled by either of the following methods. ? comparison of the toc pin voltage with the pwm oscillator waveform this method determines the low side ou tput transistor duty accord ing to the result of comparing the toc pin voltage with the pwm oscillator waveform. the pwm duty will be 0% when the toc pin voltage is under about 1.3 v and will be 100% when that voltage is over about 3.0v. since the toc pin is the output of the ctl amplifier, a control voltage cannot be directly input to the toc pin. accordingly, the ctl amplifier is normally used as a full feedback amplifier (by connecting the ei ? pin to the toc pin) and inputting a dc voltage to the ei pi n (here the toc voltage will be equal to the ei + pin voltage). when the ei + pin voltage increases, the output duty will increase as well. since the motor will be driven if the ei + pin is in the open state, a pull-down resistor should be connected to the ei + pin in applications where this is not desirable. a low level must be input to the pwmin pin (or it must be connected to ground) if the toc pin voltage control system is used. ? pwmin pulse input a 15 to 25khz frequency pulse signal can be input to the pwmin pin and the low side output transistor duty can be controlled based on the duty of that input signal. when the pwmin pin is low, the output will be on, and when high, the output will be off. when the pwmin pin is open, the in put will go to the high level and the output will be off. if pwmin pin control is used, the ei ? pin must be connected to ground and the ei + pin must be connected to the toc pin.
lb11693h no.a0287-12/24 12. undervoltage protection circuit the undervoltage protection circuit turns off the low side output transistor if the lvs pin voltage falls below the circuit's opera ting voltage (about 3.8v). this operating voltage is the detection level for a 5v system. the detection level can be increased by connecting a zener diode in series with the lvs pin to apply a level shift to the detection level. the current flowing into the lvs pin during detection is about 65a. to suppress variations in the zener voltage, it is necessary to stabilize the rise of the zener diode voltage by increasing the current that flows in the zener diode. if this is necessary, insert a resistor between the lvs pin and ground. when the lcs pin is open, it will be pulled to the ground le vel by the built-in pull-down re sistor and the output will be turned off. thus if the undervoltage protection circuit is not used, a voltage in excess of the release voltage (about 4.3v) must be applied to the lvs pin. note that the maximum rating for the lvs pin voltage is 30v. 13. motor constraint protection circuit when motor motion is constrained, the external capacitor connected to the csd pin will be alternately charged (up to about 3.0v) with a constant current of about 2.4a and discharged with a constant current of about 0.17a (to about 1.0v). thus the csd pin voltage will have a sawtooth waveform. the motor constraint protection circuit turns the motor (the low side output transistor) on or off repeatedly based on this sawtooth waveform. motor drive will be on during the period the csd pin external capacitor is being ch arged from about 1.0v to about 3.0v and will be off when it is being discharged from about 3.0v to about 1.0v. the drive on/off operation protects the ic and the motor when the motor is physically constrained from moving. if a 0.47f cap acitor is connected to the csd pin, the ic will iterate an on/off cycle in which drive is on for about 0.4 seconds and off for about 5.5 seconds. while the motor is turning, the csd pin voltage will be held at a certain voltage (that depends on the motor speed) by (a) a csd pin external capacitor discharge operation based on about 10s discharge pulses generated internally in the ic when the hall input in1 switches (that is, on rising and falling edges on the fg output) and (b) a charge operation on that capacitor by a constant current of about 2.4a. since the hall input in1 does not switch when the motor is physically constrained, th e discharge pulses are not generated and the csd pin external capacitor will be charged to about 3.0v by the constant current of about 2.4a. the motor constraint protection circuit operat es when the capacitor reaches about 3. 0v. the constraint protection operation will be released when the motor constraint is released. if the motor speed is extremely low, the csd pin voltage during that motor rotation will be held at a comparatively high voltage, and if that voltage reaches about 3.0v, the constr aint protection function will operate. since the constraint protection function will operate if the ha ll input in1 frequency falls below about 10hz, caution is required when using the motor constraint protection circuit with motors that will operate at low speeds. connect the csd pin to ground if the motor constraint protection circuit is not used.
lb11693h no.a0287-13/24 test circuits i cc 1, i cc 2 v o sat1 , v o sat2 set the switch sw on when measuring i cc 1. set the switch sw off when measuring i cc 2. input the logic states shown in the table so that the output transistor for the corresponding phase is on. after setting the switch sw to position 1 for source transistor meas urement or to position 2 for sink transistor measurement, proceed to the measurement itself. v o sat = v o source + v o sink the figure shows the circuit used for measuring out3. use similar circuits for measurement of the other p hases.
lb11693h no.a0287-14/24 i o leak vd1, vd2(ex, out1) after setting the logic state so th at the high and low side output transistors for the corresponding phase are in the off state, proceed to the measurement itself. set the switch sw to position 1 for source transistor leakage measurement, and to position for sink transistor leakage measurement. the figure shows the circuit used for measuring out3. use similar circuits for measurement of the other p hases. input the logic states shown in the table so that the output transistor for the corresponding phase is off. set i o to 0.7a when measuring vd1. set i o to 1.5a when measuring vd2. the figure shows the circuit used for measuring out1. use similar circuits for measurement of the other phases.
lb11693h no.a0287-15/24 vreg, vreg1, vreg2 i b (ha) the figure shows the circuit used for measuring in3. use similar circuits for measurement of the input pins for the other phases.
lb11693h no.a0287-16/24 v oh (csd), v ol (csd) i csd 1, i csd 2 change v in from 0.8v to 2.0v when measuring i csd 1. change v in from 3.3v to 2.0v when measuring i csd 2.
lb11693h no.a0287-17/24 v sd l, v sd h, v sd v rf after manipulating the logic and setting values such that v o is less than 2v when v cc = vm, proceed to the measurement itself.
lb11693h no.a0287-18/24 v io (ctl), i b (ctl), v oh (ctl), v ol (ctl) v oh (pwm), v ol (pwm), v(pwm), i chg (pwm) set the switch sw to the 2 position when measuring v oh (ctl). set the switch sw to the 1 position when measuring v ol (ctl). refer to the figure below. record the ipwm current when vpwm is changed from 1.0 to 2.1v as ichg.
lb11693h no.a0287-19/24 f(pwm) v ol (rd), i l (rd) after power is first applied, set v in to the ground level. set the switch sw to position 1 and measure v ol (rd). then set v in to 3.3v. set the switch sw to position 2 and measure i l (rd).
lb11693h no.a0287-20/24 v ol (fg), i l (fg) i fgfil 1, i fgfil 2 after power is first applied, set v in 1 to 3v and v in 2 to 2v. set the switch sw to position 1 and measure v ol (fg). then set v in 1 to 2v and v in 2 to 3v. set the switch sw to position 2 and measure i l (fg). when measuring ifgfil1, set v in 1 = 3v, v in 2 = 2v, and vfgil from 0.5 to 2.0v. when measuring ifgfil2, set v in 1 = 2v, v in 2 = 3v, and vfgil from 3.5 to 2.0v.
lb11693h no.a0287-21/24 v ih (s/s), v il (s/s), v io (s/s), v is (s/s), i ih (s/s), i il (s/s) after manipulating the logic and setting values such that v o is less than 2v when v s/s = 0v, proceed to the measurement itself. ic operation is ok as l ong as the output voltage changes when v s/s is between 1.0 and 2.0v. v ih (s/s) v il (s/s)
lb11693h no.a0287-22/24 v ih (pi), v il (pi), v io (pi), v is (pi), i ih (pi), i il (pi) after manipulating the logic and setting values such that v o is less than 2v when v pi = 0v, proceed to the measurement itself. ic operation is ok as l ong as the output voltage changes when v pi is between 1.0 and 2.0v. v ih (pi) v il (pi)
lb11693h no.a0287-23/24 v ih (fr), v il (fr), v io (fr), v is (fr), i ih (fr), i il (fr) after manipulating the logic and setting values such that v o is less than 2v when v fr = 0v, proceed to the measurement itself. ic operation is ok as l ong as the output voltage changes when v fr is between 1.0 and 2.0v. v ih (fr) v il (fr)
lb11693h ps no.a0287-24/24 on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability ar ising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorize d for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other appli cation in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws a nd is not for resale in any manner.

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